Frequency synthesizers are commonly used to generate signals with one or more desired frequencies from a single fixed-frequency reference signal. The signals generated by frequency synthesizers may be used, for example, for the transmission and reception of radio frequency (RF) signals. To reduce the frequency of a reference signal, frequency synthesizers perform frequency division. This frequency division may be performed at integer values or fractional values. Performing frequency division at integer values is significantly less complex than doing so at fractional values. However, many applications demand fractional frequency division.
There are several conventional circuit topologies for performing both integer and fractional frequency division. However, these conventional circuit topologies generally suffer from slow start up times, high power consumption, and high jitter. While more recent developments to the conventional circuit topologies for fractional frequency division have focused on fixing one or more of the above problems, these conventional circuit topologies are often overly complex, relying on techniques such as multi-phase input clocking.
In light of the above, there is a need for frequency synthesizer circuitry that is capable of performing fractional frequency division with a fast start up time, low power consumption, low jitter, and reduced complexity.